Up until now, there has been discussed reducing the warpage of a board at the time of soldering electronic components to the board in order to realize excellent soldering, high-density mounting, reliability, or the like. Further, there has been discussed providing a semiconductor device improved in mounting yield and connection reliability or the like. Further, there has been discussed suppressing the deformation of a circuit board and enhancing the performance and reliability of a hybrid integrated circuit. Further, there has been discussed providing a plastic package for a semiconductor that realizes its lightweight and thinning and reduces its warpage due to a change in temperature. Further, there has been discussed providing a tape type ball grid array semiconductor device capable of improving the reliability of connection by solder balls and reducing distortion generated on the solder balls according to a method in which a difference in thermal expansion between a tape type wiring board and an external board when a semiconductor package is heated is decreased and the generation of the warpage of the tape type wiring board is suppressed.
Patent Document 1: Japanese Laid-open Patent Publication No. 2007-88293
Patent Document 2: Japanese Laid-open Patent Publication No. 11-40687
Patent Document 3: Japanese Laid-open Patent Publication No. 02-079450
Patent Document 4: Japanese Laid-open Patent Publication No. 10-56110
Patent Document 5: Japanese Laid-open Patent Publication No. 10-150117